DIVMODE=div
Control and status register
| EN | Enable the PWM channel. |
| PH_CORRECT | 1: Enable phase-correct modulation. 0: Trailing-edge |
| A_INV | Invert output A |
| B_INV | Invert output B |
| DIVMODE | 0 (div): Free-running counting at rate dictated by fractional divider 1 (level): Fractional divider operation is gated by the PWM B pin. 2 (rise): Counter advances with each rising edge of the PWM B pin. 3 (fall): Counter advances with each falling edge of the PWM B pin. |
| PH_RET | Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. |
| PH_ADV | Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) |